Following the trend of manufacturing lighter, thinner, shorter and smaller integrated circuits, scale-down of elements for improving degree of integration is under way.
To meet the micronization of element, technologies for forming thin junctions and thin insulation films operable under low voltage is required for forming transistors.
Consequently, even a common MOSFET (Metal On Semiconductor Field Electron Transistor), due to the decrease of gate width following adoption of LDD (Lightly Doped Drain) structure, exhibits defects like short channel effect showing both decrease of threshold voltage and weakening of punch through characteristic, and increased leakage current due to DIBL (Drain Induced Barrier Lowering) showing lowered voltage barrier between a source diffusion layer and a substrate by an electric field of drain.
Therefore, as a solution about these defect, substrate engineering which could protect threshold voltage and sub threshold characteristics while maintaining surface temperature by forming high density impurities as a punch through stopper inside of the substrate where drain depletion regions would develop, is under way.
On the other hand, problems of thermal degradation of element characteristics by hot carrier effects in which electrons are injected into a gate oxide film due to increased average energy of electrons and sudden elevation of electron temperature due to a horizontal direction electric field on a channel near drain.
To prevent such hot carrier effects, it is necessary to increase the density of low density impurity regions(n-) in a LDD structure to improve current driving capacity while relieving the electric field, but, because in which case short channel effects increase significantly, it is difficult to satisfy both suppressing short channel effects and improving current driving capacity on the same time.
Such a foregoing conventional transistor is to be explained hereinafter, referring to attached drawings.
FIG. 1 explains an inversion layer formation in a channel region of a conventional transistor, FIGS. 2a-2c explain in of a relation of drain voltage and a conduction channel of a conventional transistor, and FIG. 3 shows characteristic curves of a conventional enhancement type n-type MOSFET, wherein a structure of a conventional enhancement type n-type transistor, as shown in FIG. 1, includes high density n type impurity regions having high impurity density, each connected to a source pole and a drain pole, and formed in a certain interval on a p-type silicon substrate having low impurity density and resistivity of 1 to 10 .PHI./cm, a thin gate insulation film(oxide film) of about 200 Angstroms thick covering, the surface of the p-type silicon substrate between the high density n-type impurity regions, and gate poles of polysilicon film or layers of polysilicon films and silicide films formed on the gate insulation film.
Operation of a conventional thin film transistor having foregoing construction is to be explained hereinafter.
Referring to FIG. 1, when positive voltage is applied on a gate pole, because an electric field is concentrated on within the gate insulation film the resistance of the gate insulation film is much greater than the resistance of semiconductor.
Therefore, the electric field formed the positive voltage applied on the gate pole, pushing holes being minority carriers and pulling electrons, is converted into a n-type region in which the electrons out number the holes on the surface of p-type silicon substrate, inducing an inversion layer.
That is, an electron layer forms a conduction channel between a drain region and a source region, being a high density n-type impurity regions.
A gate voltage required to cause such a conduction channel is called threshold voltage.
Shown in FIGS. 2a-2c are a conversion into a conduction channel when a gate voltage and a drain voltage are applied, wherein a voltage between the gate pole and source VGS is supposed to be kept to a constant value higher than the threshold voltage VT, the electric potential difference between the p-type silicon substrate and source is VSS, and the electric potential difference between the source and the drain is VDS. Shown in FIG. 2(a) is when the VDS is relatively low at VSS=0, wherein, because the conduction channel width of the source side corresponds to VGS and the conduction channel width of the drain side corresponds to VGS-VDS, it can be known that the conduction channel width of the drain side becomes narrower than the conduction channel width of the source side.
Shown in FIG. 2(b) is when the conduction channel of the drain side is pinched-off, wherein VGS-VDS=VT, therefore VDS=VGS-VT(VSS=0) in pinch-off.
And shown in FIG. 2(c) is beginning of forming of a depletion region between the drain and the conduction channel when the VDS exceeds the pinch-off voltage, wherein, because resistance of a depletion region is much more greater than the resistance of a conduction channel, the excessive voltage ((VDS--VDS)(pinch-off) exceeding the pinch-off is applied to the depletion region along the interface, therefore, though the depletion region increases following the elevation of VDS, a drain current ID substantially maintains the same value.
That is, shown in FIG. 3 is current-voltage characteristics of an enhancement type n-channel MOSFET, wherein, though VDS is elevated, the drain current is of a saturated current.
However, the foregoing conventional transistors lave had problems of having a deterioration of operative characteristic and a drop of reliability of a transistor due to drop of threshold voltage, weakening of punch through characteristic and increase of leakage current due to increase of short channel effects and hot carrier effects by the shortened conduction channel between a source and a drain following the decrease of size of a transistor according to the progress of high integration of semiconductor element.